The invention generally relates to polishing pads for chemical mechanical polishing (CMP), in particular, the invention relates to polishing pads for electrochemical mechanical polishing (ECMP), including methods and systems therefor.
In the fabrication of integrated circuits and other electronic devices, multiple layers of conducting, semiconducting, and dielectric materials are deposited on or removed from the surface of a semiconductor wafer. Thin layers of conducting, semiconducting, and dielectric materials are deposited by a number of deposition techniques. Common deposition techniques include physical vapor deposition (PVD), also known as sputtering, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and electrochemical plating (ECP).
As layers of materials are sequentially deposited and removed, the uppermost surface of the wafer becomes non-planar. Because subsequent semiconductor processing (e.g., lithography) requires the wafer to have a flat surface, the wafer needs to be planarized. Planarization is useful in removing undesired surface topography and surface defects, such as rough surfaces, agglomerated materials, crystal lattice damage, scratches, and contaminated layers or materials.
CMP is a common technique used to planarize substrates such as semiconductor wafers. In conventional CMP, a wafer carrier or polishing head is mounted on a carrier assembly and positioned in contact with a polishing pad (e.g., IC1000™ and OXP 4000™ by Rohm and Haas Electronic Materials CMP, Inc. of Newark, Del.) in a CMP apparatus. The carrier assembly provides a controllable pressure to the wafer, pressing it against the polishing pad. The pad is optionally moved (e.g., rotated) relative to the wafer by an external driving force (e.g., a motor). Simultaneously therewith, a polishing fluid (e.g., a slurry or reactive liquid) is flowed onto the polishing pad and into the gap between the wafer and the polishing pad. The wafer surface is thus polished and made planar by the chemical and mechanical action of the pad surface and polishing fluid.
Currently, there is a demand in integrated circuit (IC) manufacturing for increased densities of wiring interconnects necessitating finer conductor features and/or spacings. Further, there are increasing uses of IC fabrication techniques using multiple conductive layers and damascene processes with low dielectric constant insulators. Such insulators tend to be less mechanically robust than conventional dielectric materials. In manufacturing ICs using these techniques, planarizing the various layers is a critical step in the IC manufacturing process. Unfortunately, the mechanical aspect of CMP is reaching the limit of its ability to planarize such IC substrates because the layers cannot handle the mechanical stress and heat buildup during polishing. In particular, delamination and fracture of the underlayer cap and dielectric material occur during CMP due to frictional stress induced by the physical contact between the polished substrate and the polishing pad. In addition to the frictional stress, unwanted excess heat is produced by the physical contact, providing, for example, poor polishing results.
To mitigate detrimental mechanical effects associated with CMP such as those described above, one approach is to perform ECMP. ECMP is a controlled electrochemical dissolution process used to planarize a substrate with a metal layer. The planarization mechanism is a diffusion-controlled adsorption and dissolution of metals (e.g., copper) on the substrate surface by ionizing the metal using an applied voltage. In performing ECMP, an electrical potential must be established between the substrate and the polishing pad to effectuate electrodiffusion of metal atoms from the substrate metal layer. This can be done, for example, by providing an electrical current to the substrate carrier (anode) and the platen (cathode).
Jacobsen et al., in U.S. Pat. No. 3,504,457 discloses a stacked pad having a poromeric polishing layer 20 overlying an inert layer 35, for polishing semiconductor wafers. Unfortunately, inert layer 35 acts to insulate the adhesive 40 from the polishing layer 20 and the slurry. In other words, inert layer 35 has poor electrical conductivity and is ineffective for use in ECMP. In addition, inert layer 35 has poor thermal conductivity and will suffer from the excess heat buildup, as discussed above. Hence, what is needed is a polishing pad that overcomes the above noted deficiencies. Namely, what is needed is a polishing pad for ECMP that provides improved electrical and thermal capabilities and control.